This seems to put the controller in AHCI mode. If so, I would start with the first patched ROM the one that sets df[1: The sum of all bytes in the file should be 0x There were problems with OSX with the first patch which is why the second one exists. I think what you want is to change b1 02 to b1 Anyway, you can erase the flash chip, so that no option ROM is executed and the card is rendered non-bootable anymore. I replaced 3 bytes with b1 02
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How can I update bios?
I also used pcicfg in DOS to check the card was detected. Linux sets register 40 bit 2 to enable the IDE port?
JMicron JMB vs. P35 express SATA controller? – Ars Technica OpenForum
Why can it be?. I want to use latest bios because it will be better 1. I did not experiment with the values of these bits except for toggling bit 6. Anyway, you can erase the flash chip, so that no option ROM is executed and the card is rendered non-bootable anymore. Change three instances of b1 jnb363 to b1 Those connected at boot were not detected.
Why do you want to avoid the on-board SATA controller? Trying to do that in the option Cnotroller causes a several-minute hang during boot when loading the option ROM again, seemingly waiting for a disk and giving upeven when a PATA disk is present.
Controlper is done the same way as with any other disk. Please work with the latest bios and share it. Can you work that changes at latest bios ver 1. I have read through this page and start to comprehend the edits needed.
It would be great if you can test it.
The sum of all bytes in the file should be 0x Could you pass on a link please of your setup? Unfortunately, I do not know enough about hex editing to find where to patch. Register Function 43 Defaults to 0x Thus it seems like setting 0x41[7: Only cntroller register df[1: Sorry, forgot to update CRC. Header Type ‘non-bridge’ single-func Vendor: What am I missing?
JMicron JMB363 vs. P35 express SATA controller?
It is not a data table containing some form of initial register values. I speculate its purpose is to disable the option ROM, allowing the main BIOS to set up the rest of the device configuration without interference. Or cohtroller there any trick?
There were problems with OSX with the first patch which is why the second one exists. I tried modifying the option ROM to also configure register 0x to this value, but had many problems booting. These configuration registers seem to control the hardware directly. I had some help from the option ROM release noteswhich gave some hints as to what the PCI config registers do or at least, supposed to do after being interpreted by the option ROM.
You know if it is possible?. Register df is used by the option ROM code at offset 0x This changes mov cl, 0x02 to mov cl, 0x